In present semiconductor technology, CMOS devices such as n-FETs and p-FETs are typically fabricated upon semiconductor wafers that each has a substrate surface oriented along one of a single set of equivalent crystal planes of the semiconductor material (e.g., Si) that forms the substrate. In particular, most of today's semiconductor devices are built upon silicon wafers having wafer surfaces oriented along one of the {100} crystal planes of silicon.
Electrons are known to have a high mobility along the {100} crystal planes of silicon, but holes are known to have high mobility along the {110} crystal planes of silicon. On one hand, hole mobility values along the {100} planes are roughly about 2 to 4 times lower than the corresponding electron mobility values along such planes. On the other hand, hole mobility values along the {110} silicon surfaces are about 2 times higher than those along the {100} silicon surfaces, but electron mobility along the {110} surfaces are significantly degraded compared to those along the {100} surfaces.
As can be deduced from the above, the {110} silicon surfaces are optimal for forming p-FET devices due to the excellent hole mobility along the {110} planes, which leads to higher drive currents in the p-FETs. However, such surfaces are completely inappropriate for forming n-FET devices. The {100} silicon surfaces instead are optimal for forming n-FET devices due to the enhanced electron mobility along the {100} planes, which results in higher drive currents in the n-FETs.
In typical CMOS circuits, complementary n-FETs and p-FETs are provided side-by-side. For example, FIG. 1 shows CMOS static random access memory (SRAM) cells, each of which comprises two n-FETs that function as pass-gate transistors (PA), two n-FETs that function as pull-down transistors (PD), and two p-FETs that function as pull-up transistors (PU). Since the pass-gate transistors (PA) and the pull-down transistors (PD) are both n-FETs, they are formed within the same active region (A1). The pull-up transistors (PU), which are p-FETs, are formed in a different active region (A2) that is isolated from A1 by trench isolation regions. Gate structures (G) are arranged above various active regions to form gates for the FETs, where channel regions of the FETs are located directly under the gate structures (G) in the active regions.
The n-FET active region A1 and the p-FET active region A2 are located side-by-side in the substrate along line I-I, as shown in FIG. 1. On one hand, if the substrate surface is oriented along one of the {110} planes of silicon, the device performance of the pull-up transistors (PU), which are p-FETs, are enhanced, but the device performance of the pass-gate transistors (PA) and pull-down transistors (PD), which are both n-FETs, are degraded. On the other hand, if the substrate surface is oriented along one of the {100} planes of silicon, the device performance of the pass-gate transistors (PA) and pull-down transistors (PD) are enhanced, but the device performance of the pull-up transistors (PU) are degraded.
There is therefore a need for providing a semiconductor substrate having different surface orientations (i.e., hybrid surface orientations) for enhancing the device performance of SRAM cells or like devices that comprise both n-FETs and p-FETs.
A need also exists to provide an integrated semiconductor device that is located on a substrate with hybrid surface orientations and comprises at least a first FET (i.e., either an n-FET or a p-FET) and a second, complementary FET (i.e., either a p-FET or an n-FET). The first and second, complementary FETs have hybrid channel orientations, i.e., the channel of the first FET is oriented along a first set of equivalent crystal planes that provide relatively higher carrier mobility in the first FET, and the channel of the second, complementary FET is oriented along a second, different set of equivalent crystal planes that provide relatively higher carrier mobility in the second, complementary FET.